Electrodepositing a metal in integrated circuit applications

ABSTRACT

A method is described in which a contact hole to an interconnect in an insulating layer is fabricated. A barrier layer is subsequently applied. Afterward, a photoresist layer is applied, irradiated and developed. With the aid of a galvanic method, a copper contact is then produced in the contact hole. Either the barrier layer or an additional boundary electrode layer serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production.

PRIORITY AND CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. Ser. No. 11/136,582filed May 23, 2005, which is a continuation of International ApplicationNo. PCT/DE03/03845 filed Nov. 20, 2003, which claims priority to Germanapplication 102 54 815.3 filed Nov. 23, 2002, all of which areincorporated herein in their entirety by reference.

BACKGROUND

1. Field of the Invention

The present invention relates to the field of the application of metalor a metal alloy in the fabrication of an integrated circuitarrangement, and more particularly, it relates to a method forelectrodepositing a copper metal.

2. Description of the Related Art

Requirements for an increased performance of semiconductor chips lead toever higher packing densities in addition to ever higher currentdensities in metallization planes or metallization layers of anintegrated circuit (e.g., power semiconductors configured to switch anumber of amperes). Problems due to electromigration and heating come tothe fore and limit the performance of the components. By way of example,copper or copper alloy have been used in place of conventional tungstenor aluminum. Copper enables higher current densities and a thermalconductivity by a factor of 2. Due to the high diffusion coefficient ofcopper silicon, however, copper also increases risks to the transistorplanes. A diffusion of copper atoms into the active regions alters, forexample, the threshold voltage, the channel length or the switching timeof a transistor. The diffused atoms may act as a defect, a center forcharge carriers, generation or recombination, cause a shortening of thelifetime of charge carriers, and/or introduce oxidation induced stackingfaults and weak points in thin oxide layers. Accordingly, a failure of atransistor may occur. Accordingly, it is necessary to prevent thediffusion of copper atoms or other atoms having a large diffusioncoefficient in silicon. The barrier layer alone is not sufficient forthis purpose, because it is also described to prevent a copper crosscontamination within the production line.

BRIEF SUMMARY OF THE INVENTION

By way of introduction only, a method for the application of a metal, inparticular of copper or a copper alloy is described, including uses ofthe method and an integrated circuit arrangement.

A plurality of contact holes to interconnects of a metallization layermay be produced in an insulating layer of an integrated circuitarrangement. A barrier layer is subsequently applied, for example bybeing sputtered on. A contact hole is also referred to as a via, if itdoes not lead directly as far as a semiconductor carrier substrate ofthe integrated circuit arrangement. The contact hole has e.g. a diameterwhich is significantly less than 1 μm (micrometer) or which is greaterthan 1 μm or even greater than 10 μm.

The barrier layer increases the adhesion between the metal and theinsulating layer and may provide a diffusion barrier for the atoms ofthe metal. Atoms may be prevented from penetrating into active regionsof the semiconductor carrier substrate due to the large diffusioncoefficient of the atoms, and from unintentionally altering theelectrical properties of integrated semiconductor components there.

The foregoing summary is provided only by way of introduction. Thefeatures and advantages of the personalized marketing architecture maybe realized and obtained by means of the instrumentalities andcombinations particularly pointed out in the claims. Nothing in thissection should be taken as a limitation on the claims, which define thescope of the invention. Additional features and advantages of thepresent invention will be set forth in the description that follows, andin part will be obvious from the description, or may be learned bypractice of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C show fabrication stages in the fabrication of a coppermetallization in accordance with a first method variant with an aluminumnucleation layer,

FIGS. 2A to 2C show fabrication stages in the fabrication of a coppermetallization in accordance with a second method variant with a barrierlayer as nucleation layer, and

FIG. 3 shows an integrated circuit arrangement fabricated by a flip chiptechnique.

DETAILED DESCRIPTION OF THE INVENTION

A method for electrodepositing a metal will now be described more fullywith reference to the accompanying drawings. In each of the followingfigures, components, features and integral parts that correspond to oneanother each have the same reference number. The drawings of the figuresare not true to scale.

In semiconductor production, in which copper may be used inmetallization planes, it is desired to separate a Front End Of Line(FEOL) production and a Back End Of Line (BEOL). FEOL productionrelates, inter alia, to method steps for fabricating Shallow TrenchIsolation (STI), Local Oxidation of Silicon insulations (LOCOS), thefabrication of transistors, including the required implantations. BEOLproduction relates, inter alia, to the fabrication of metallization andpassivation planes. By way of example, if only the last metallizationlayer is fabricated using a metal whose atoms have a large diffusioncoefficient in silicon, then BEOL production is again subdivided intotwo subareas. The subdivision leads to technical dedication in respectof installations. This means that a contaminated installation isprevented for processes in which a cross-contamination between differentinstallations is critical. The installation is often spatially separatedfrom other production areas.

In an exemplary method, a metal or a metal alloy is applied with the aidof a galvanic processes. In a first embodiment, a barrier layer providesa boundary electrode in the galvanic process for the application of themetal or the metal alloy. In a second embodiment, in addition to thebarrier layer, before the application of a radiation sensitive layer, aboundary electrode layer is applied, which does not contain a metalwhose atoms have a large diffusion coefficient in silicon, or which isnot a metal alloy in which more than 5% of the atoms have a largediffusion coefficient in silicon, and which includes a material having adifferent material composition than the barrier layer. The methodutilizes a galvanic deposition of the metal which is suitable both fordepositing relatively small layer thicknesses of between 30 nm and 300nm, by means of a method free of external current, or a method usingexternal current, and also for depositing relatively large layerthicknesses.

Layer thicknesses of greater than 1 μm or greater than 10 μm can beproduced by a method using external current or in a combined galvanicmethod. However, the method according to the invention uses a boundaryelectrode layer whose atoms have a small diffusion coefficient insilicon (i.e. precisely do not have a large diffusion coefficient insilicon). This provides the advantage, for example, that a lithographicmethod for defining the position of the metal structures that are to beproduced galvanically can be carried out, if appropriate up to theremoval of resist, completely by machines which, when carrying out themethod, are not contaminated with the metal of which the galvanicallydeposited metal layer is composed. These installations are thereforeavailable to production without any restriction.

In the exemplary first embodiment, the barrier layer is used as aboundary electrode layer and an additional boundary electrode layer doesnot have to be applied. Contamination problems are significantlyreduced, or eliminated during the application of the barrier layer andof the radiation-sensitive layer.

In the exemplary second embodiment, however, a boundary electrode layeris applied in addition to the barrier layer. This results in a degree offreedom, namely the choice of the material of the boundary electrodelayer. Through the use of a suitable material, the galvanic method canbe carried out in a simpler manner than without the use of an additionalboundary electrode layer, in particular with regard to the requirementsmade of complying with process parameters. In order that nocontaminations occur during the application of the boundary electrodelayer and during the application of further layers, for example aradiation sensitive layer, the boundary electrode layer comprises ametal whose atoms have a small diffusion coefficient in silicon, i.e.precisely do not have a large diffusion coefficient D in silicon.

In one development, a radiation sensitive layer may be applied after theapplication of the barrier layer. The radiation sensitive layer isirradiated according to a pattern, and the radiation sensitive layer isdeveloped after irradtiation. A metal or a metal alloy is applied intoregions that are free of the radiation sensitive layer after thedevelopment, with the aid of a galvanic method. Residues are removedfrom the radiation sensitive layer after the application of the metal orthe metal alloy. Electrodeposition may also be effected over the wholearea of the boundary electrode layer, after which, for example, achemical mechanical polishing method (CMP) is then performed.

In another development, the metal or metal alloy that is galvanicallyapplied may have a large diffusion coefficient in silicon. The diffusioncoefficient of the atoms of the metal is e.g. greater than 10⁻⁹ cm²/s at400° C. Thus, the following holds true for copper for a temperature T inthe range of between 400° C. (degrees Celsius) and 900° C.:

D[cm ² /s]=4.7 10⁻³exp (e _(a) /kT),

where e_(a) is the activation energy in eV (electron volts), in thiscase 0.43 eV, and k is Boltzmann's constant.

The same applies to a metal alloy to be applied galvanically in whichmore than 5% by weight, more than 50% by weight or even more than 90% byweight of the atoms have a large diffusion coefficient in silicon. Theadditions often have only a small proportion of e.g. less than 5% byweight. As an alternative, however, a different metal or a differentmetal alloy may also be deposited galvanically, e.g. comprising amaterial having a small diffusion coefficient, e.g. aluminum. If amaterial having a large diffusion coefficient is subsequently depositedonto this material, then the same considerations as explained aboveapply with regard to the contamination.

In another development, the galvanic process is carried out using anexternal current or voltage source. The external current or voltagesource leads to a higher deposition speed. In addition, reducing agentsand catalysts are added to the galvanic bath in the case of a methodusing external current.

In another development, a galvanic method free of external current iscarried out. The deposition rate for a layer thickness of one micrometeris furthermore in the minutes range and is e.g. less than 10 minutes.However, distortions of the electric field as occur in the case of amethod with an external current or voltage source are avoided. A metallayer of uniform thickness is produced as a result. The crystal latticethat forms during the galvanic method free of external current becomesmuch more uniform in comparison with the galvanic method with anexternal current or voltage source, and also more homogeneous on accountof the longer time for the deposition. This reduces the electricalresistance of the layer, so that less heat is generated with the currentflow remaining the same. In addition, the more homogeneous crystallattice is more resistant to electromigration. These technicalproperties are all the more important the higher the current intensitiesto be switched.

In a second aspect, the invention also relates to a method for theapplication of metal by means of a galvanic method free of externalcurrent. The galvanic layer deposited in a manner free of externalcurrent is particularly dense and particularly uniform. The resultingimproved electrical properties of the galvanic layer deposited in amanner free of external current in comparison with a deposition usingexternal current, in particular the lower electrical resistance and theresistance to electromigration, are of particular importance for manyapplications, (e.g. in contact holes at locations at which the currentdensity is very high). The barrier layer is used as a boundary electrodelayer and an additional boundary electrode layer does not have to beapplied. Alternatively, a boundary electrode layer may be applied inaddition to the barrier layer to provide a degree of freedom, namely inthe choice of the material of the boundary electrode layer. Through theuse of a suitable material, the galvanic method can be carried out in asimpler manner than without the use of an additional boundary electrodelayer with respect to the barrier layer.

In one development of the method in accordance with the second aspect,use is made of a metallic boundary electrode layer whose atoms have alarge diffusion coefficient in silicon, or a metal alloy layer in whichmore than 5% of the atoms have a large diffusion coefficient in silicon.As an alternative, the boundary electrode layer used is a layer which isnot a metal layer of said type or a metal alloy layer of said type, forexample a barrier layer or a boundary electrode layer applied inaddition to the barrier layer.

In a next development of the method in accordance with the first aspector of the method in accordance with the second aspect, the material ofthe boundary electrode layer has a lower potential in theelectrochemical series and the galvanically deposited metal or thegalvanically deposited metal alloy. The electrochemical series specifiesthe voltages established in different materials if the latter arecombined with a reference electrode, namely a hydrogen electrode, toform a galvanic cell. The following hold true, by way of example:

-   Li−3.04 V (volts),-   Al−1.66V,-   Ti−1.628 V,-   Ni−0.23 V,-   H₂−0 V,-   Cu+0.35 V,-   Ag+0.8 V,-   Hg+0.85 V,-   Pt+1.2 V-   Au+1.41 V.

By way of example, it holds true for copper Cu that, with fewexceptions, e.g. for gold Au, for platinum Pt, for mercury Hg and forsilver Ag, virtually all the metals are oxidized in the presence ofcopper ions, metals that are more electronegative going into a solutionand the dissolved copper ions being deposited as a metallic coating.

Therefore, in one development, an electrolyte solution used for thegalvanic method contains metal ions, in particular copper ions. Thesolution may be based on water, alcohol, ether, or any combinationthereof. Further additions may not be necessary for an electrochemicaldeposition on account of the potential difference (i.e. in particular noreducing agents such as formaldehyde or any catalysts for aprecipitation reaction).

The electrolyte solution may contain only a small number ofconstituents, for example only the molecules of the basic solution (e.g.water molecules, the metal ions and ions of opposite polarity which forma salt with the metal ions, said salt being dissolved in the electrolytesolution). On account of the electrodeposition as a result of potentialdifferences, neither the temperature nor the pH of the electrolytesolution are critical in the galvanic method free of external current.By way of example, the method is carried out at room temperature, i.e.at 20° C. for example. Heating the electrolyte solution accelerates thedeposition, but leads to more rapid evaporation of the solvent, and thusto an alteration of the concentrations in the electrolyte solution.Cooling below the temperature mentioned leads to a more uniform layergrowth, but to a slower deposition rate.

In a method free of external current, depending on the salt used, the pHof the electrolyte solution lies in the range from 1 to 6, i.e. in theacidic range, for example, when using copper sulfate CuSO₄, or in therange of between 8 and 14, i.e. in the basic range, for example, whenusing copper hydroxide Cu(OH)₂.

The boundary electrode layer applied in addition to the barrier layermay be decomposed completely or as far as a partial layer during thegalvanic method. The barrier layer may be decomposed in a partial layer.The remaining part of the barrier layer still ensures a sufficientdiffusion barrier.

An etching operation may also be carried out after the removal of theradiation-sensitive layer, during which etching operation the barrierlayer is etched in accordance with the metal structures produced duringthe electrodeposition, preferably in a simple wet-chemical etchingprocess.

The interconnect may contain aluminum or an aluminum alloy, for examplealuminum with a small addition of silicon or copper, e.g. of one percent by weight. The methods according to the invention are particularlysuitable for fabricating the topmost metallization layer. By way ofexample, the lower metallization layers comprise aluminum or an aluminumalloy which contains more than 90% by weight, or more than 95% by weightof aluminum (i.e. a readily processable material).

The barrier layer may also contain, for example, tungsten, titanium ortantalum (i.e. metals having a melting point of greater than 1600° C.).In one refinement, a nitride layer of such a metal is also used. Thesebarrier layers are particularly suitable as a diffusion barrier andadhesion-promoting layers.

The boundary electrode layer additionally applied to the barrier layermay also include aluminum or an aluminum alloy which contains e.g. morethan 90% by weight or more than 95% by weight of aluminum (i.e. amaterial that can readily be processed in terms of process engineering).

The galvanically deposited metal may be copper, gold, silver orplatinum. Metal alloys with a plurality of these substances are alsoused.

The contact hole may have a diameter greater than 1 μm (micrometer),greater than 10 μm or even greater than 20 μm. In one refinement, thelayer thickness of the deposited layer is greater than 100 nm(nanometers) or greater than 500 nm or even greater than 10 μm, if amethod using external current is utilized for the electrodeposition.However, contact holes having a diameter of less than 1 μm can alsoreadily be produced by means of a method free of external current, ifappropriate in combination with an external current method.

The method may be applied to fabricate an integrated power circuitthrough which currents of greater than 1 A (ampere), greater than 10 Aor even greater than 100 A flow during switching. In particular, withthe use of electrodeposition methods free of external current, it ispossible to produce electrical connections with a very low electricalresistance and high resistance to electromigration, as are required forsuch high currents.

In another application, the exemplary method serve to fabricate aplurality of carrier circuits and to fabricate a plurality of carriedcircuits. A plurality may include, by way of example, a productionquantity of several thousand circuits. A carried circuit is applied on acarrier circuit with the aid of a chip rapid-mounting technique. Thistechnique is also referred to as a flip-chip technique. By way ofexample, the two circuits are soldered such that their active sides faceone another. As an alternative, it is also possible to use other fixingmethods of the flip-chip technique.

In additional, an integrated circuit arrangement having a contact holecontaining a metal or a metal compound whose atoms have a largediffusion coefficient in silicon is provided. The metal or the metalcompound has a crystal lattice homogeneity as arises only during agalvanic deposition method free of external current. As a result, theelectrical properties of the contact are considerably better incomparison with contacts which have been sputtered or fabricatedgalvanically with the aid of an external current or voltage source.

FIGS. 1A to 1C illustrate fabrication stages for a last metallizationlayer of an integrated circuit arrangement 10 in accordance with a firstmethod variant. The integrated circuit arrangement 10 includes at leastone metallization layer 12, in which a plurality of aluminuminterconnects are arranged, for example an interconnect 14. After thefabrication of the metallization layer 12, an insulating layer 16 isdeposited. The insulating layer may be silicon dioxide or aborophosphosilicate glass (BPSG) material.

Using photolithography, a plurality of contact holes (i.e. vias), arethen produced in the insulating layer 16, for example a contact hole 18leading to the interconnect 14.

A barrier layer 20 is subsequently deposited, where the barrier layerincludes, for example, tungsten-titanium WTi or nickel Ni. The barrierlayer 20 was applied for example with the aid of a sputtering method andhas a thickness of less than 100 nm (nanometers).

An aluminum nucleation layer 22 is then applied, for example with theaid of a sputtering method. The aluminum nucleation layer 22 includesaluminum Al and has a thickness of 50 nm, for example, in the exemplaryembodiment. In other exemplary embodiments, the thickness of thenucleation layer 22 is likewise less than 100 nm.

As illustrated in FIG. 1B, a photoresist layer 30 is subsequentlyapplied. The photoresist layer may be 30 μm (micrometers) or more inthickness. The photoresist layer 30 is exposed and developed inaccordance with predetermined mask structures, where it being possibleto utilize installations which have not been contaminated with copperand are also not contaminated with copper.

After the patterning of the photoresist layer 30, an electrodepositionmethod free of external current is performed using a copper sulfatesolution CuSO₄. In this case, a copper contact 32 is deposited in thecontact hole 18 and above the contact hole 18. During theelectrodeposition, the aluminum nucleation layer 22 is decomposed in theregion of the contact hole 18. The barrier layer 20 is decomposed onlyin an upper partial layer, so that it function as a diffusion barrier toa sufficient extent.

At the end of the method free of external current, the copper contact 32does not project or projects only slightly into the lower part of thecutout contained in the photoresist layer 30. If the contact hole 18 hasalready been filled at the end of the method free of external current,the electrodeposition is ended. By contrast, if the contact hole 18 hasstill not been filled at the end of the method free of external current,or if the copper contact is intended to project further beyond theinsulating layer 16, then a method using external current is used forfurther electrodeposition. As an alternative, electrodeposition is alsoeffected only by means of an external current method.

As illustrated in FIG. 1C, residues of the photoresist layer 30 aresubsequently removed. Afterward, by means of a wet-chemical etchingmethod or by means of a dry etching method, the aluminum nucleationlayer 22 is removed in regions which are not covered by the coppercontact 32. Likewise by means of a wet-chemical etching method or bymeans of a dry etching method, the barrier layer 20 is removed inregions which are not covered by the copper contacts (e.g. by the coppercontact 32).

The method explained with reference to FIGS. 1A to 1C can be carried outwith a comparatively or relatively thin barrier layer 20. Thisfacilitates the process implementation. By way of example, a thinbarrier layer adheres better than a thicker barrier layer.

FIGS. 2A to 2C show fabrication stages in the fabrication of a coppermetallization directly on a barrier layer. As illustrated in FIG. 2A, anintegrated circuit arrangement 10 a contains a metallization layer 12 a.The metallization layer 12 a contains an interconnect 14 a made ofaluminum. An insulating layer 16 a comprising the same material as theinsulating layer 16 was applied to the metallization layer 12 a.Afterward, the insulating layer 16 a was patterned with the aid of aphotolithographic method, a contact hole 18 a having been produced abovethe interconnect 14 a.

A barrier layer 20 a was subsequently applied. The barrier layerincludes, for example, a double layer of titanium Ti and titaniumnitride TiN. The thickness of the barrier layer 20 a is such thattensile stresses are minimized and that, on the other hand, however, asufficiently thick layer is also present after a partial decompositionof the barrier layer 20 a in a galvanic method free of external current.

As illustrated in FIG. 2B, a photoresist layer 30 a is subsequentlyapplied to the barrier layer 20 a. The photoresist layer 30 a has, forexample, a thickness of 30 μm. The photoresist layer 30 a is thenexposed and developed in a photolithographic method, installations whichhave not been contaminated with copper and are also not contaminatedwith copper again being used.

Afterward, a copper contact 32 a made of copper Cu is produced in theregion of the contact hole 18 a (e.g. with the aid of anelectrodeposition method free of external current). An upper partiallayer of the barrier layer 20 a decomposes during the electrodeposition,see broken line 50.

As illustrated in FIG. 2C, the residues of the photoresist layer 30 aare subsequently removed, for example, by means of a wet-chemicalcleaning step. In a wet-chemical etching process, the barrier layer 20 ais then removed in regions which are not covered by the copper contact32 a.

As an alternative, only a galvanic method using external current or acombined method is used in the method explained with reference to FIGS.2A to 2C as well.

FIG. 3 shows an arrangement 100 comparing an integrated processorcircuit 102 and two integrated memory circuits 104 and 106. Thearrangement 100 is arranged on a printed circuit board 110, connectingwires 112 and 114 leading from the processor circuit 102 to the printedcircuit board 110.

The integrated circuit arrangements 102 to 106 have been fabricated bymeans of the method explained with reference to FIGS. 1A to 1C or bymeans of the method explained with reference to FIGS. 2A to 2C. Afterthe fabrication of the integrated circuits 102 to 106, the two memorycircuits 104 and 106 were soldered to the processor circuit 102 using aso-called chip rapid-mounting technique (flip chip technique), seesoldering points 120 to 126. An adhesive bonding technique can be usedas an alternative. The active sides of the memory circuits 104 and 106face the active side of the processor circuit 102.

The arrangement illustrated in FIG. 3 can be fabricated viably in largenumbers when the method according to the invention is used to fabricatethe integrated circuits 102 to 106. In the case of other methods, thecontamination of installations would no longer be tenable.

The process implementation explained above introduces advantages forproviding aluminum processing methods that are standard processes inBEOL. In addition, existing installations and processes may be utilizedwithout any restriction and dedication of exposure installations may beeliminated. The methods may reduce costs. The methods may provide aclear separation between FEOL and BEOL with little or no risk ofcontamination, and higher flexibility and modularity.

1. A method for the application of metal in which the following methodsteps are performed without any restriction by the order specified:production of a contact hole to an interconnect in an insulating layeror an integrated circuit arrangement, application of a barrier layerafter the production of the contact hole, application of a metal or ametal alloy with the aid of a galvanic method, the barrier layer servingas a boundary electrode in the galvanic method for the application ofthe metal or the metal alloy, or, in addition to the barrier layer,before the application of the radiation-sensitive layer, a boundaryelectrode layer being applied having a different material compositionthan the barrier layer, wherein a solution used for the galvanic methodcontains copper ions, and wherein the solution is free of a reducingagent.
 2. The method as claimed in claim 1, characterized by thefollowing steps: application of a radiation-sensitive layer after theapplication of the barrier layer, irradiation of the radiation-sensitivelayer in accordance with a pattern, development of theradiation-sensitive layer after the irradiation, removal of residues ofthe radiation-sensitive layer after the application of the metal.
 3. Themethod as claimed in claim 1, wherein the atoms of the metal have alarge diffusion coefficient in silicon, or wherein in the metal alloymore than 50 of the atoms have a large diffusion coefficient in silicon.4. The method as claimed in one of claim 1, wherein the galvanic methodis carried out using an external current or voltage source.
 5. Themethod as claimed in one of claim 1, wherein the galvanic method iscarried out in a manner free of external current.
 6. The method asclaimed in claim 1, wherein the solution is prepared on the basis ofwater, alcohol, ether or a mixture of said substances.
 7. The method asclaimed in claim 6, wherein the electrolyte solution is of formaldehyde.8. The method as claimed in claim 1, wherein the boundary electrodelayer is completely decomposed, or decomposed as far as a partial layer,during the galvanic method, wherein the barrier layer is decomposed in apartial layer during the galvanic method.
 9. The method as claimed inclaim 1, wherein, after the removal of the radiation-sensitive layer, anetching operation is carried out in which the barrier layer is etched inaccordance with the metal structures produced.
 10. The method as claimedin claim 9 wherein the barrier layer is etched in accordance with themetal structures produced in a wet-chemical etching process or withoutcarrying out a further lithographic method.
 11. The method as claimed inclaim 1, wherein the interconnect comprises aluminum or an aluminumalloy.
 12. The method as claimed in claim 1, wherein the barrier layercontains a metal having a melting point of greater than 1600° C., orwherein the barrier layer contains a metal whose atoms have a smalldiffusion coefficient in silicon, or wherein the barrier layer containsa nitride, or wherein the barrier layer comprises a nitride, or whereinthe barrier layer contains one or more of the substances tungsten,nickel, tantalum, tantalum nitride, titanium or titanium nitride, orwherein the boundary electrode layer comprises aluminum or an aluminumalloy.
 13. The method as claimed in claim 1, wherein the metal iscopper, gold, silver or platinum, or wherein the metal alloy containsmore than 40% by weight of at least one of said substances.
 14. Themethod as claimed in claim 1, wherein the contact hole has a diameter ofgreater than 1 μm, or wherein the layer thickness of the galvanic layeris greater than 100 nm.
 15. The method as claimed in claim 1, whereinthe diffusion coefficient of the atoms of the metal or of atoms of themetal alloy in silicon at 400° C. is greater than 10⁻¹² cm²/s.
 16. Theuse of the method as claimed in claim 1 for fabricating an integratedcircuit arrangement which switches currents of greater than 1A, or theuse of the method for fabricating a multiplicity of carrier circuits andcarried circuits, in each case at least one carried circuit beingarranged on a carrier circuit, and sides with active components beingassigned to one another using a chip rapid mounting technique.
 17. Theuse of the method as claimed in claim 1, wherein sides with activecomponents are assigned to one another by soldering the carried circuitand the carrier circuit.
 18. An integrated circuit arrangementfabricated by the method of claim 1, having a contact hole filled with ametal or a metal alloy, wherein the metal or the metal alloy has,completely or within a partial layer, a crystal lattice homogeneity asis produced during a galvanic deposition method free of externalcurrent.